Single Event Hardening Latch Design in 65 nm Technology

With technology scaling, single event induced soft error has become an important threat to circuit’s reliability. A single event hardening latch design is proposed based on SMIC 65 nm CMOS technology. First, C-elements which have the function of holding state were used and cascaded into two levels to tolerate single event upset. Then a delay element was embedded in the latch and combined cascaded C-elements to constitute time redundancy to tolerate single event transient. Finally, a circuit based on Schmitt trigger was chosen as delay element. The experimental results show that the proposed latch has no sensitive node to common mode fault, and tolerates single event transient on clock circuit, compared to the referred hardening designs. It also achieves 30.58% reduction in layout area, 44.53% reduction in power, and 26.51% reduction in power of clock circuit, all on average. Moreover, its power is insensitive to process, supply voltage and temperature variations.