An Accelerated Ray Tracing Algorithm for the Intel^® Xeon Phi^TM Architectures

To accelerate ray-box intersection tests and speed the ray tracing in photorealistic rendering, a novel parallel ray tracing algorithm based on Intel many integrated cores(MIC) is presented in this paper. At the stage of scene preprocessing, this algorithm constructs a bounding volume hierarchy(BVH) with a branching factor of 4 which well adapts to the architecture of MIC. While tracing rays, the algorithm uses CPU to control the entire pipeline. Specifically, it adopts the optimized multi-threads scheduling strategy to schedule the coprocessor MIC to conduct ray-box intersection tests, asynchronously transmits data between CPU and MIC, and well exploits and utilizes the computing power of both CPU and coprocessor. Furthermore, we propose a parallel intersection algorithm to accelerate ray-box intersection tests. It takes full advantage of MIC's wide SIMD processing unit that it applies vectorization operations to take 4 ray-box intersections at the same time. Experimental results show that, compared with the native CPU implementation, the algorithm presented in this paper is 2~4 times faster at testing the ray-box intersections, ending up with a well accelerated ray tracing rendering process.