SCANGIN: An Approach for Reducing Dynamic Power Dissipation in Scan Test

This paper proposes an approach to eliminate unnecessary transitions on scan chains during scan-in phase.By using scan cells reordering in combination with logic gate insertion,it reduces scan-in power dissipation.Experimental results on ISCAS'89benchmark circuits show that the proposed approach can reduce peak power dissipation by 94.5% during scan test and average power by 93.8%,with ignorable area overhead.