Optimizing Test Access Architecture by Genetic Algorithm

Test access is a main issue encountered in the core-based system-on-chip (SOC) design. For an embedded core, which is deeply embedded in the system chip, direct physical access to its peripheries is not available by default; hence, additional access mechanisms are required. An approach based on genetic algorithm is proposed to deal with several issues related to the design of optimal test access mechanisms that minimize test time of SOC, including the assignment of cores to test buses, and distribution of test data width between multiple test buses. As a case study, the test access mechanisms of two hypothetical but nontrivial systems are optimized by our approach. Experiment results show that the proposed algorithm performs better in global optimum searching than the existing method based on integer linear programming (ILP).