A Test Pattern Selection Method of Dynamic Burn-In for Logic Circuits

Towards the requirement on input patterns of logic circuits for dynamic burn-in application, this paper proposes an input pattern selection method to self-heat the CUTs. The candidate input pattern set is generated by ATPG tools with transition fault model. The power weights of the different types of gate with various input combinations are investigated to lead to more accurate results. According to the result of logic simulation, a power weight is introduced to describe the power consumption of CUTs. Then the optimal pattern sequence is selected using a genetic algorithm directed by the power weight with a Hamilton Loop model. Experimental results on ISCAS’85 benchmark circuits show that, in comparison with the pattern pair to generate the maximum power dissipation, the pattern sequence generated can reduce the number of non-transition nodes while sustaining high burn-in power dissipation, which can make the power more uniform in the CUTs.