STUDY AND IMPLEMENTATION ON A DYNAMIC TIMING VERIFICATION SYSTEM HHTVS-D

This paper describes a dynamic timing verification system, which is an important part of the High-Speed Hardware Timing Verification System. In the system a six-valued simulator, and a simulative model with delays are used, thus rising delays and falling delays can be dealt with separately. All paths or critical paths can be found automatically with S-C input test vector. The system can detect timing errors report the path with the errors,and display the timing chart in circuits.