Memory Optimizing Scheme and FPGA Implementation of Bit Plane Encoder

A memory optimizing subblock-based scheme for bit plane encoder(BPE) of JPEG2000 is presented to solve the mismatch problem in access pattern to code block memory existing in traditional schemes.In new scheme,a policy of subdividing a code block into 4×4 subblocks which are encoded independently is employed.Compared with traditional schemes,proposed scheme reduces the interval of encoding two consecutive bits of a coefficient from 3N²Δt to 48Δt,and decreases the amount of accessing code block memory from(3K-2)N² to N²/W.New scheme not only has excellent compatibility with existing accelerating technologies,but also exploits the parallelism among subblocks.A sample-parallel and subblock-parallel BPE architecture is implemented in FPGA.It can improve the encoding time from O(N²) to O(N),and save the status memories by more than 39%.Experimental results show that our design outperforms existing fastest architecture by 1.3X.