TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORK

Zhang Yang; Wu Chang; Zhao Li; Yan Xiaolang

Zhang Yang, Wu Chang, Zhao Li, Yan Xiaolang. TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORKJ. Journal of Computer-Aided Design & Computer Graphics, 1995, 7(2): 141-146.

Citation:

Zhang Yang, Wu Chang, Zhao Li, Yan Xiaolang. TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORKJ. Journal of Computer-Aided Design & Computer Graphics, 1995, 7(2): 141-146.

Citation:

Zhang Yang, Wu Chang, Zhao Li, Yan Xiaolang. TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORKJ. Journal of Computer-Aided Design & Computer Graphics, 1995, 7(2): 141-146.

TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORK

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TLU-Based FPGA is a very popular FPGA architecture. In this paper, we present an improved algorithm for single-output combinational network, which integrates the advantages of the area-driver Chortle-crf and the delay-driver Chortle-d.This makes it possible for the extension of our algorithm to multiple-output combinational network and even sequential network.

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TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORK

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