A RESEARCH ON THE HIGH-LEVEL VHDL BEHAVIOR MODEL OF MULTI-STAGE PIPELINE STRUCTURE
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Abstract
To model a digital system behaviourally by VHDL on the high level is the basis on which a VLSI is designed by auto-synthesis system with the method of Top-Down.In this paper,the research on how to model a multi-stage pipeline structure behaviourally by VHDL on the high-level is given by taking the RISC SPARC MB86901 as an example and some associated problems have also been treated.
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