A Test Case Generation Method at Register Transfer Level

As a primary part of design verification and chip testing in the life cycle of Integrated Circuits (ICs), test generation receives increasing attention. By the application of branch coverage, bit-function coverage and statement-observability coverage measures, this paper introduces a high level test case generation method based on Control Flow Graph/Data Flow Graph (CFG/DFG) model, and then puts forward a feasible test generation method at Register Transfer Level (RTL). Experimental results demonstrate that the method can produce shorter test sequence in less time, and obtains an equal or a little less stuck-at fault coverage at gate-level. Furthermore, the method provides sufficient flexibility due to the adoption of test case technique.