A Hybrid Direct-Iterative Parallel Matrix Solving Algorithm for Post Layout Circuit Simulation

With the process node continually scaling down, circuit performance degradation becoming more and more dramatic due to parasitic elements. Post layout circuit simulation is now an indispensable flow in analog/mixed signal design. But post layout circuit simulation usually increases tens even hundreds of times comparing with pre-layout simulation because of the huge amount of parasitic elements. Matrix solving is the most time consuming part in post layout circuit simulation. This paper proposed a novel hybrid direct-iterative parallel method which could significantly reduce matrix solving time. The proposed method used hyper graph partition technology to partition the circuit into several coupling sub-circuits. LU decomposition and GMRES were used to solve the corresponding internal and coupling equations. This paper then proposed an effective preconditioned GMRES method by utilizing the physical characteristics of fast nodes and power girds. The method had been successfully implemented in Huada's circuit simulator ALPS. The experimental results demonstrated the effectiveness of the proposed method.