A STUDY OF ALGORITHMS FOR VALIDATING LOGIC CONDITIONS AMONG FSM STATES

Finite state machine (FSM) is a reflection of VLSI control path, and its automatic synthesis becomes a very important step of design automation (DA). In this paper, we will discuss the problem of validating logic conditions among FSM states in the input phase of FSM automatic synthesis process, analyse the interaction between validations of logic conditions among FSM states, and propose a optimal algorithm for validating logic conditions among FSM states that will decrease the time complexity and be easy to implement. Finally, the flowchart of our optimal algorithm and some experimental results are also presented in this paper.