Design of High-Speed Self-Acknowledgement Asynchronous Dual-Rail Push Channel

This paper proposes a novel high-speed asynchronous dual-rail push channel for the data transmission with varying transmission rate in globally asynchronous locally synchronous network-on-chip.With the self-acknowledgement control,the forward latency is reduced and the throughput is improved.Meanwhile,the asynchronous channel transmits dual-rail data through two independent transmission link with symmetric structure in order to avoid complex timing design,reduce transmission link interference and ensure reliable data transmission.Performance of four-stage channel has been verified under different fabrications and temperatures based on SMIC 0.18 μm standard CMOS technology.Simulation results show that the forward latency is 70 ps,the average dynamic power dissipation is 2.71 mW with the throughput of 4.46 GHz,which can fulfill the requirements of high-speed,low power,highly robust on-chip communication.