Synthesis System of Deep-Sub-Micron Cell-Level CMOS Analog Circuit

A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper. In the system, the operating point of the circuit and the small signal parameters of MOS transistor are calculated more accurately, and the circuit performance equations are generated from its topology automatically in order to improve the equation-based method. At the same time, manufacturability is taken into account to make the synthesized circuit still meet specifications when parametric fluctuations in the manufacturing process and the variance in their operating conditions occur. It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.