Deterministic Diagnosis Pattern Generation for Scan Chain Faults

Scan is a widely used design-for-testability technique to improve test and diagnosis quality.Recent industry data reports that scan chain and its control logic could take as much as 30% silicon area,meanwhile,the scan chain failures account for almost 50% of chip failures.In this paper,we proposed a deterministic scan chain diagnosis pattern generation algorithm.Firstly,a circuit model is built for scan chain fault diagnosis.Based on this model,any existing stuck-at fault pattern generation tool can be employed to generate patterns.And then a fault response analysis method is proposed to reduce the number of candidate fault pairs so as to benefit the diagnosis timing overhead without any penalty on diagnosis quality.Experimental results show that the proposed algorithm outperforms previous approaches on fault diagnosis accuracy,resolution and diagnosis time.