Multi-Level Logic Synthesis and Automatic Generation of Logic Diagrams

This paper presents multilevel logic synthesis and automatic generation of netlists and logic diagrams. The algorithm of multilevel logic synthesis and the algorithm of placement and routing for logic diagrams automatic generation are given. The method of how netlists are generated and how interface forms are transfered from netlists to logic circuits description language are described. The logic diagrams automatic generation under Xwindow circumstance from netlists are introduced.