Fast Placement Algorithm for Hierarchical FPGAs

As the capacities of the FPGA devices continue to grow,and more complex architectures are embedded into modern FPGAs,it brings great challenges to FPGA physical design tools.In this paper,a fast placement algorithm is proposed to new commercial hierarchical FPGAs.The algorithm is based on partition framework,and embedded with some optimization strategies aiming at global placement process and detailed placement process on hierarchical FPGAs.Experimental results show that the embedded optimization strategies enable our algorithm a great improvement to the total wirelength of circuit,which achieves 29% on average.While compared with clustering-based algorithm,our algorithm speeds mount up to over 4 times in runtime with nearly 40% reduction on wirelength.