Hardware Accelerator and 3D Pixel Shader Architecture for Computer Graphics

To meet the increasing demand for graphics accelerator in smart hand phone and network notebook,a preliminary architecture for 2D graphics accelerator and 3D pixel shader is presented.The architecture includes a VLIW instruction set,a reconfigurable data driven pipeline and micro-engines.Instead of using traditional parallel processing and task partition scheme,a new memory task mapping method is proposed,which may dynamically assign the task for each scan-line to the micro-engines.In order to assess the efficiency of the architecture,the performance simulation platform,system simulation platform and RTL simulation platform are built.The simulation results show that the new method can be used to improve the utilization of computational resources and reduce frame buffer memory access conflict.In addition,the paper also discusses the structure of graphics generation unit,image transformation unit,the VLIW micro-engine shader,and the relevant graphics acceleration algorithms.