The Overlap-Combination Approach to 3D Chip-Level Capacitance Extraction and Its Parallel Implementation

A two-direction overlap-combination method is adopted to implement the chip-level capacitance extraction while using the 3D hierarchical block boundary element method as field solver.The proposed method cuts a chip into a great deal of small-scale regions,and then combines the capacitance matrices for all regions to get the full capacitance matrix.The computational accuracy and speed of the overlap-combination method are also analyzed,and parallel experiments were carried out. Numerical experiments with actual layout structures show that the proposed method is effective,reliable and with high parallelity.