Building Resilient NoC with a Reconfigurable Routing Algorithm
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Graphical Abstract
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Abstract
Network-on-chip(NoC) has become an attractive structure to replace the bus to provide on-chip communication for multi-core and many-core chips due to its high bandwidth and scalability.Unfortunately,modern chips are more prone to faults with the shrinking of chip feature size.To provide reliable on-chip communication,this paper proposes a low cost and reconfigurable routing algorithm.This algorithm assumes that failed routers and links are included into rectangular faulty blocks without shared boundaries,and classifies faulty blocks according to their relative position to network edges.For each type of faulty blocks,the proposed algorithm defines a way to update the status of routers.Reconfigured NoC could tolerate unbounded number of arbitrarily distributed router and link failures.Unlike existing fault-tolerant routing algorithms,the proposed keeps the network free of deadlock without adding extra virtual channels.Therefore,it is more cost efficient.Extensive simulations validated that the proposed routing algorithm is quite suitable for core-to-cache and cache-to-cache NoCs.
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