Design for High-Speed Circular FIFO

This paper proposes a novel circular FIFO used in multiprocessor system-on-chip(SoC) for the data transfer between different time domains in globally asynchronous locally synchronous systems.With the transmission mode combining both serial and parallel communication,data of different widths can be sent and received quickly by the circular FIFO handled under special operation protocol.Meanwhile,the data integrity is ensured during the communication by the two-rail encoding transfer manner.Based on SMIC 0.18 μm CMOS technology,simulation results have shown that the delay is 681ps with the average energy consumption of 6.45 pJ for one transfer request responded,which can meet the requirements of high speed,low power,strong robustness and good reusability in the design of multiprocessor SoC and network-on-chip.