The Algorithm and Design for Hardware Tessellator

Surface tessellation is a technique that subdivides a patch of surface into convex polygons,which can be rendered using standard graphic routines.Tessellator is an important part of tessellation.It is also one stage of Direct3D 11 pipeline.This paper presents a novel and optimal algorithm for hardware tessellator,which can tessellate a quad or triangular primitive patch.The algorithm consists of inner subdivision,outer band subdivision and parametric coordinate generation.The inner subdivision can be configured to balance the computation quantity between block partitions and mesh subdivision.The outer band subdivision can realize alternate increment of node index on inner and outer edges.Parametric coordinate generation can translate node index into corresponding parametric coordinate in its domain.The algorithm can be implemented by fixed point addition and comparison operations.Multiplication and division are used only in the initialization of the algorithm.The paper also proposes a hardware implementation of the tessellator,which employs a fully pipelined and parallel architecture.The results of simulation validate the algorithm and show high performance of the design.