Low Power Deterministic Test Scheme Based on Viterbi

With the development of integrated circuit manufacturing technology, chip test has become a focus of concern. For the problem of a large amount of test data volume and high test power consumption, this paper proposes a low power test compression scheme based on Viterbi algorithm. Firstly, a few don’t care bits（X bits） in test cubes are used to reduce test power, for enhancing the consistency between adjacent bits of the cube. Then in order to increase the number of X bits and improve the encoding efficiency of Viterbi compression, lots of specified bits are encoded to X bits again by compatible block code. Finally, use Viterbi algorithm to compress the test cube set after coding. This paper presents a test process that can solve the problems of test compression and test power at the same time. The experimental results show that the scheme not only obtains better test compression ratio, but also reduces the test power consumption effectively. The average power consumption is reduced by 53.3%.