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Zhao Zihao, Chu Zhufei, Wang Lunyao, Xia Yinshui. Power Optimization of Multi-Level MPRM Logic Circuits[J]. Journal of Computer-Aided Design & Computer Graphics, 2024, 36(4): 615-624. DOI: 10.3724/SP.J.1089.2024.19951
Citation: Zhao Zihao, Chu Zhufei, Wang Lunyao, Xia Yinshui. Power Optimization of Multi-Level MPRM Logic Circuits[J]. Journal of Computer-Aided Design & Computer Graphics, 2024, 36(4): 615-624. DOI: 10.3724/SP.J.1089.2024.19951

Power Optimization of Multi-Level MPRM Logic Circuits

  • In this paper, multi-level mixed-polarity Reed-Muller (MPRM) power optimization is addressed by tabular technique and onset table methods. The low-power model of multi-input AND/XOR gates and tabular technique enable us to traverse the optimal power circuit of the two-level MPRM under all polarities for each cut set of the circuit. The onset table is then used to optimize multi-level MPRM based on two-level MPRM circuits. Based on our experimental results on the MCNC and EPFL benchmark suites, our algorithm improved power by 49.90% and 27.87% respectively, compared to the original circuit. Compared to the two-levels MPRM power optimization algorithm, the average area optimization rate of our algorithm is 20.52%, and the average power optimization rate is 21.24%.
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