Parallel Logic Simulation for Functional Test

To improve the efficiency of functional test simulation in digital systems with good performance scalability, an algorithm of parallel logic simulation is proposed. By tailoring to the architectural feature of graphics cards and multi-core microprocessors in heterogeneous computing, the algorithm combines task parallelism in gate evaluation at the same level and a race-tolerant mechanism for event management. It makes use of bitwise logical operation-based gate evaluation, frame-based simulation, and VCD-based functional test stimulus. Experiments are conducted on open-source circuits of openMSP and ISCAS89 with over one million gates. Compared to the single-threaded algorithm, a performance speedup of 8.9 to 86.8 can be achieved; moreover, the speedup is proportional to the size of the circuit.