Design and Implementation of VLSI for Finite State Entropy Encoding

The Zstd(Zstandard)lossless compression algorithm that implemented by software is difficult to meet the demand of compression speed in specific application field when processing massive data.It is an effective solution to this problem by using the hardware acceleration scheme,especially for the hardware acceleration of FSE(finite state entropy).Thus,a hardware implementation of the compression and decompression in FSE is proposed for Zstd.This scheme determines the optimal hardware acceleration step by fixing the size of compression table,reduces the storage space and improves the transmission speed by adding hardware modules of sequence mapping,enhances the time of parallel processing by dividing the seven-stages of flow and realizes the architecture by software and hardware collaboration.The proposed architecture is implemented in the TSMC 55 nm process,and the highest frequency can reach 750 MHz.The experimental results show that compared with the software implementation,the speed of the whole compression is more than 9 times faster,the speed of the whole decompression is more than the 100 times faster.