Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology

With continuous scaling of CMOS technology,single event multi-node upset induced by charge sharing effect has become an important factor affecting chip reliability.This paper proposed a novel multi-node upset(MNU)tolerant latch design:LPMNUHL.Based on DICE latch,where single node upset is resilient,the latch builds a mechanism of triple modular redundancy and uses a voter as output.The proposed latch is tolerant to multi-node upset and votes the correct output logic value.What’s more,there is no high impedance state in the latch and soft errors of the internal nodes can be blocked successfully.The latch can not only tolerance triple node upset completely,but also tolerance 90.30%of quadruple node upset.Due to the use of a high-speed transmission path,the clock-gating technology and a clock-gating voter,the proposed latch is low power.In 32 nm CMOS technology,extensive SPICE simulation results demonstrate that compared with the previous latches,the proposed latch has an average delay reduction of 40.16%,an average power reduction of 44.96%,an average power delay product reduction of 65.40%,and an area reduction of 34.60%.Moreover,the proposed latch is not sensitive to temperature and voltage variations.