Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology

The charge sharing effect of nanoscale CMOS technology is becoming more and more significant, and the probability of multiple nodes upset simultaneously caused by particle incidence increases sharply. In order to improve the reliability of sequential units, a triple node upsets(TNUs) self-recovery hardened latch structure is proposed. By using the blocking ability of dual input inverters, and placing 24 dual input inverters into six stages, the upset nodes are recovered correctly by feedback;In addition, the internal asymmetric connection mode is used to eliminate the common mode fault;and the driving ability of NMOS/PMOS in the dual input inverter is optimized, which can eliminate the metastable state caused by the inversion of the node logic value. Experiments with Hspice show that, compared with the existing four types of hardened latches that tolerate TNUs, only the proposed structure and TNURL can self-recover from TNUs. The other three hardened latches cannot recover from TNUs by itself, and will produce a high impedance state at the output;Compared with the TNURL structure, the power consumption of the proposed structure is reduced by 35.3%, the delay is reduced by 48.3%, and the power delay product is reduced by 67.6%.