Low-Power Radiation Hardened 12T Memory Cell Design in 65 nm CMOS Process

As the size of CMOS processes continues to shrink,memory cells become more sensitive to high-energy radiation particles,and the resulting soft errors and double node upset caused by charge sharing increase dramatically.To improve the reliability of memory cells,a radiation hardened 12T memory cell consisting of 4 PMOS transistors and 8 NMOS transistors is proposed,moreover,N1,N2 and N3 and N4 in the NMOS transistor constitute a stack structure to reduce the power consumption of the memory cell;which avoids negative transient pulses generated by storage nodes based on upset physical mechanism,the negative feedback introduced between storage nodes effectively hinders the memory cell upset.Extensive HSPICE simulation results show that the proposed memory cell can not only fully tolerate the upset of sensitive nodes,but also partially tolerate the sensitive node pair upset caused by charge sharing.Compared with other memory cells,the power consumption,area overhead,read time and write time of the proposed memory cell are reduced by 18.28%,13.18%,5.76% and 22.68% on average,and the value of the noise margin is larger,the results show that the proposed memory cell make better tradeoff among area overhead,access time,power consumption and stability.