Dynamic Stratifying and Its Applications in Defect-Tolerant Mapping Optimization for CMOL Circuits

Due to high defect rate in CMOS/nanowire/molecular hybrid (CMOL) circuits, defect-tolerant mapping is essential to solve the practical application of CMOL circuits. For the time-consuming and difficulty to map large circuits in traditional whole defect-tolerant methods, a defect-tolerant mapping optimization method based on dynamically stratifying CMOL circuit is proposed. Firstly, circuit defect types are classified. Then, the CMOL circuit is dynamically stratified by the decreasing number of the defects. Finally, modified Tabu search algorithm is employed to verify the performance of the proposed method in the stratified CMOL circuit. The experiment results of the ISCAS benchmarks show that compared with existing methods, the proposed method has advantages in terms of wirelength and CPU time.