A Global Layout Algorithm Based on Key Gates within Segments of CNFET Circuits

Carbon nanotube field-effect transistors (CNFETs) are considered the most promising alternative to conventional silicon-based CMOS devices. However, influenced by the variation of carbon nanotube (CNT) density in CNFET devices, traditional silicon-based circuit layout methods often exhibit poor timing yields on CNFET circuits. To solve this problem, this paper first proposes a statistical delay model for segments; and on this basis, a global layout algorithm based on key gates within segments is proposed for the asymmetric spatial correlation of CNFET circuits. The experimental results show that the algorithm can effectively improve the circuit timing yield and significantly outperforms the existing algorithms in terms of execution time, revealing its potential for application in large-scale circuits with high timing yield requirements.