Abstract:
As the area and power consumption of TP RAM in So C are large,a new design method of optimization is proposed.In order to achieve the function of the original TP RAM and keep the external interface unchanged,TP RAM is replaced with SP RAM,and read-write interface logics of conversion are added around SP RAM.The method proposed in this paper is used in the multi core So C chip which has been successfully taped out in TSMC 28 nm HPM process.The chip occupies 10.7 mm×11.9 mm of die area and consumes 17.2 W.The testing results indicate that the area of optimized RAMs is reduced by 24.4%,and the power saving is 39%.