Abstract: This paper presents an analytical placement algorithm to handle large-scale FPGAs design fast.Motivated by the idea in large ASIC design,the algorithm uses nonlinear wire-length as objective and takes FPGAs special structure in account.A nonlinear programming is solved to get the cell position by a conjugate gradient method with less iterations to reduce the runtime of the combinatorial optimization.Experimental results show that this approach can effectively reduce runtime and improve placement quality.And the final wire-length results compared to FastPlace also testify its reasonable quality.