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庞子涵, 周强, 高文超, 郭世一, 钱旭. FPGA物理不可克隆函数及其实现技术[J]. 计算机辅助设计与图形学学报, 2017, 29(9): 1590-1603.
引用本文: 庞子涵, 周强, 高文超, 郭世一, 钱旭. FPGA物理不可克隆函数及其实现技术[J]. 计算机辅助设计与图形学学报, 2017, 29(9): 1590-1603.
Pang Zihan, Zhou Qiang, Gao Wenchao, Guo Shiyi, Qian Xu. Hardware Implementation of Physical Unclonable Function on FPGAs[J]. Journal of Computer-Aided Design & Computer Graphics, 2017, 29(9): 1590-1603.
Citation: Pang Zihan, Zhou Qiang, Gao Wenchao, Guo Shiyi, Qian Xu. Hardware Implementation of Physical Unclonable Function on FPGAs[J]. Journal of Computer-Aided Design & Computer Graphics, 2017, 29(9): 1590-1603.

FPGA物理不可克隆函数及其实现技术

Hardware Implementation of Physical Unclonable Function on FPGAs

  • 摘要: 作为一种重要的硬件安全原语,物理不可克隆函数(PUF)利用集成电路不可控的制造工艺差异生成具有唯一标志的签名数据,以其特有的轻量级和防篡改属性在芯片认证、随机数产生器和密钥生成等硬件安全领域具有极大优势.现场可编程门阵列(FPGA)应用因其对电路设计可自由灵活配置的特点,自身的安全性和可靠性问题越来越受到关注.PUF技术可以从硬件层面为FPGA电路提供有效安全保护,以较少的开销获得更强的抵御安全风险能力.文中系统地分析了基于FPGA PUF的模型和相应的电路结构,总结和分析FPGA PUF电路结构在随机性、稳定性和资源消耗等性能方面的优化策略,FPGA PUF技术的主要检验评价方法以及性能对比;介绍了FPGA PUF在硬件安全领域中的典型应用.最后对FPGA PUF面临的挑战和未来趋势进行了展望.

     

    Abstract: As an important hardware security primitive, physical unclonable function(PUF) which exploits intrinsic process variation, generates unique identification signature. The properties of lightweight and unique tamper-resistant endow PUF with great advantage in hardware security fields such as random number or secret key generator. As field-programmable gate array(FPGA) application has flexible configuration circuits features, its self-security and reliability issues have gained lots of attention over the recent years. PUF technology can protect circuit configuration from the hardware level with less overhead. In this paper, we give a survey on a variety of state-of-the-art PUF implementation methods, and analyze the optimization strategy of various implementation architectures in terms of randomness, stability and resource consumption. After that we compare the performance of different FPGA PUF with the test evaluation methods and introduce its specific applications. Finally, we conclude with challenges and opportunities, and paint a blueprint for the future of FPGA PUF application in the field of hardware security.

     

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