Abstract: Last level cache pollution causes extremely severe performance degradation and energy penalty due to"memory wall"and"power wall".Hardware-only or software-only last level cache optimization methods can not effectively recognize weak locality data, which means that there is performance improvement space.For addressing above problems, this paper proposes a design of software and hardware collaborative last level cache.This approach profiles the memory behavior of different data regions in a program on runtime and dynamically set the bypass and insertion policy of data regions by corresponding interfaces. While improving the memory access performance of processors, this approach can also reduce energy consumption and improve system energy efficiency.The experimental results show that, in comparison with LRU, DIP and DRRIP, the average energy efficiency of processors is respectively improved 17.42%, 12.79% and 8.15%.