Abstract: 3-input AND/XOR gate is the basic complex gate for Reed-Muller(RM) logic circuit implementation. To cope with the issues of the present AND and XOR cascaded AND/XOR gate with long delay time and high power, a transistor-level based low power 3-input AND/XOR gate, which is implemented with hybrid logic of CMOS logic and transmit logic, is proposed. First, under 55 nm CMOS process, the circuit schematic is proposed and its layout is implemented. Then, the parasitic parameter extraction based on the circuit layout and the post-simulations under different process corners are carried out. Under typical process corners, the simulation results show that, the improvement of the proposed circuit can be up to 18.79%, 26.67% and 31.25% respectively in terms of the area, power and power delay product compared with the classical cascaded designs.