Abstract: Multi-driving and circuit loop characteristics complicate timing analysis on clock mesh networks, and so far as we known, accurate timing uncertainty on specific mesh structures can hardly be pursued by any existing qualitative or quantitative characterization in literature.A simplified on-chip variation model on mesh structure and a genetic approach to timing uncertainty problem in clock mesh network were proposed.The impacts of tremendous variation sources could be converted to delay distributions in the single level, and then added into delay distributions for input drivers in mesh structure by multi-level propagation, which helps to decouple tree and mesh structure in clock network.Based on the simplified on-chip variation model, genetic algorithm was applied to find a more reasonable timing uncertainty in clock networks by the ability of global optimization.In comparison with Monte Carlo analysis and qualitative analysis methods, experimental on mesh structure at 65nm technology node validated our proposal method.