Abstract: To reduce the huge test cost, based on on-chip virtual digitization method, a parallel test structure for analog cores in mixed-signal SoCs, which using on-chip DAC and ADC, is proposed.The proposed self-hold analog test interface (SHATI) can realize temporal storage of analog test stimuli and test responses, which eliminates the extra silicon overhead caused by DAC and ADC on each test port and enables core-level and system-level parallel test for analog cores.The pipelined parallel test structure can further reduce the waiting time of test stimuli application.Test cost of analog cores is then analyzed and its optimization model is established.Optimized test wrapper groups with minimized test cost can be obtained by proposed optimization algorithm.The experimental results show that the test accuracy error with the proposed test structure is under 0.25% and test time is optimized by 40%.