Abstract: Placement of standard cells is a key stage in very large scale integration circuit design automation. This article presents a density-driven partitioning method for standard cell 3D placement. In the partitioning method, 3D placement region is divided into grids, and the cell density of each grid is calculated. Then the standard cells are allocated into 3D space based on the cell density in each grid. The partitioning method can get an optimal partitioning result and reduced the overlaps between standard cells and fixed cells effectively. The partitioning method is integrated into a 3D placer 3D-Crust, which conducts the 3D placement in 3D-transformed benchmarks. Experimental results show that the partitioning method can effectively reduce HPWL and runtime by 60.89% and 20.54% respectively compared with the original placer.