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石伟, 沈立, 任洪广, 苏博, 王志英. 解同步电路中的功耗优化方法[J]. 计算机辅助设计与图形学学报, 2010, 22(12): 2155-2161.
引用本文: 石伟, 沈立, 任洪广, 苏博, 王志英. 解同步电路中的功耗优化方法[J]. 计算机辅助设计与图形学学报, 2010, 22(12): 2155-2161.
Shi Wei, Shen Li, Ren Hongguang, Su Bo, Wang Zhiying. An Approach of Power Optimization for De-synchronized Circuits[J]. Journal of Computer-Aided Design & Computer Graphics, 2010, 22(12): 2155-2161.
Citation: Shi Wei, Shen Li, Ren Hongguang, Su Bo, Wang Zhiying. An Approach of Power Optimization for De-synchronized Circuits[J]. Journal of Computer-Aided Design & Computer Graphics, 2010, 22(12): 2155-2161.

解同步电路中的功耗优化方法

An Approach of Power Optimization for De-synchronized Circuits

  • 摘要: 针对解同步方法设计的异步电路存在冗余功耗的问题,提出一种功耗优化的解同步异步电路设计方法.首先以迭代结构乘法器为例分析操作数及电路操作行为对异步流水线功耗的影响;然后将窄数据特性及操作行为特性引入到解同步设计方法中,其中窄数据特性用于优化数据通路,操作行为特性用于优化控制通路;最后采用该方法对异步传输触发体系结构(TTA)微处理器计算内核进行功耗优化设计.实验结果表明,结构优化后的异步TTA微处理器内核功耗明显减少,约为解同步异步内核功耗的60%.

     

    Abstract: By considering the influence of operations and operands on the power of asynchronous pipelines, an improved de-synchronization flow is proposed to resolve the power redundancy problem in conventional de-synchronized circuits.First, an iterative multiplier is used to show the power redundancy problem in detail.Then, two different schemes are utilized to optimize the data path and control path respectively.The narrow-width operand characteristic is employed to optimize the data path, while operation behaviors are analyzed to optimize the control path.At last, the proposed flow is used to reduce the power consumption in an asynchronous TTA processor core.Experimental results show that the proposed method can achieve up to 40% power reduction for the de-synchronized TTA processor core.

     

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