Abstract: Increasing complexity of modern FPGA's configurable elements raises greater challenges for packing.A novel packing algorithm CSPack based on CSP graph matching is presented.It implements circuits matching utilizing constraint satisfaction problem techniques to find sub-circuits satisfying constraints and designs a set of instructions system for mapping them into CLBs.CSPack has been used in the packing module which is part of the CAD flow for Fudan University's self-developed FPGA named FDP2008 and only needs to modify files describing configurations of different FPGAs can implement packing operations for target chips.Experimental results show that CSPack compared with T-VPack achieves 6.1% increase in timing performance and 1.4% reduction in chip area.