Abstract: A three-phase low-power topology generation algorithm for application-specific network-on-chip is proposed in this paper.Firstly, partition-driven floorplan is done to determine the cores' positions and the mapping relations between cores and switches.Then, with the area and power consuming of network components (such as switches and network interfaces) taken into consideration, the simultaneous insertion of network components is formulated as an integer linear programming (ILP) , which is solved to determine the optimal positions for switches and network interfaces.Finally, path allocation is carried out to distribute the communications among switches.The experimental results show that our algorithm can save power by 35.2% and reduce the number of hops by 5.7%.