Abstract: In gate-level circuit reliability estimation methods, the fault probability p of an elementary gate, which was commonly given by expert experience, has been modeled as the fault probability of gate oxide or input-interconnects recently.This paper first analyze the formation mechanism and action patterns of faults, the topological structure of generalized gates, and the mechanism of reliability loss by combining the layout structure information.Then we present the defect growth models of gate oxide and input-interconnects to time and the calculation method of the defect remove rate.Finally we propose the p-model of a generalized gate containing the burn-in or early failure period.The proposed p-model is applied on ISCAS85 benchmark circuits.It shows that the calculation results based on the proposed model is successfully simulated with the empirical formula, which verifies the reasonability of the proposed model.The impacts of burn-in, defect remove rate, process parameters and design parameters on circuit reliability are also analyzed.