Abstract: To guarantee the test quality,the low-power processor Godson-3 requires low test power.In this paper,based on the detailed analysis of test power consumption,we propose a low power test scheme concerning both test cost and test time.By analyzing the components of test power of the Godson-3,we found that the test power of Godson-3 is mainly contributed by the combinational logics and clock networks.In order to reduce the transitions of combinational logics and clock networks,the IP based test technology and test partitions are used.One IP can be tested separately to target the lower test power,or two identical IP can be tested concurrently to reduce test time.We also use functional clock gating cells,block-gating and X-Filling to further reduce the transitions of single IP.The costs of these technologies including area,delay and test time are analyzed with details.Experimental results show that,the maximum average test power of the single IP is reduced to 6W,which is about 40% of functional average power and can effectively guarantee the test quality.