Abstract: Test pattern compression methods can reduce the memory requirements of build-in self-test（BIST）.They are more fitting for VLSI test,and hence a clustering compression method and a novel architecture are presented for deterministic BIST test pattern compression.Clustering compression is a method which uses a greedy algorithm to divide the test pattern into several clusters,and use only one special pattern to represent each cluster.The presented architecture relies on a three-dimensional compression scheme which combines input reduction,clustering compression and rotation-based compression.Firstly,it compresses the test set of random pattern resistant faults（RPRF）by input reduction in xdirection.Secondly,it compresses the input reduction set by clustering compression in y direction.Finally,it compresses the clustered set by rotation-based compression in z direction.The rotation-based compressed set are then stored in the ROM of BIST circuit.Decompress the data set in the ROM will get all the RPRF when testing.Theoretical analysis and experimental results showed that the presented scheme can enormously reduce the hardware overhead of BIST circuit. Furthermore,the circuit under test can be testing at-speed.The compression rate of benchmark s38584 can even obtain 99.87% when applying the presented scheme.