Abstract: Compared to the Dual-Core Lock-Step technique commonly used in industry, heterogeneous parallel error detection techniques using heterogeneous cores could achieve similar error coverage with smaller area overhead, at the cost of worse error detection latency and affect the performance degradation of the main core. To avoid potential security safety risks caused by errors not detected in time, a low-latency heterogeneous architecturally parallel error detection method is proposed. First, the impact on the main core’s performance is reduced by stalling the release of physical registers while copying data of the registers. Second, to improve the performance of checker cores, the main core's control flow is used to guide the instruction fetch of the checker cores, and the program segments are divided by predicting their running time in checker cores so that the maximum error detection latency can be controlled. The proposed method was implemented using the open-source XiangShan processor as the main core, and 16 Rocket processors as the checker cores. The experimental results on benchmark programs show that, error detection can be efficiently achieved with 50% logic area overhead and 22% storage area overhead, which is significantly less than the nearly 100% area overhead of the dual-core lockstep technique, while the average performance overhead on the main core is less than 1%, and the error detection latency can be effectively controlled within 2000 clock cycles. Moreover, the average performance of the checker cores has been improved by 14.9% in comparison to the original branch prediction strategy.