Abstract: Aiming at the problem that traditional silicon-based circuit layout algorithms show low timing yields on carbon nanotube field effect transistor (CNFET) circuits with varying carbon nanotube (CNT) densities, a global layout algorithm based on the key gates in a segment is proposed. Firstly, we analyze each level of the circuit from the bottom to the top, and establish the gate delay and gate tree delay models, and then we combine the CNFET circuit correlation matrix to establish the statistical delay model of the segment with the mean and variance of the delay; then, we determine the correlation between the timing yield and the statistical delay of the segment through the theoretical analysis; finally, we use the asymmetric spatial correlation of CNFET circuits, and we use the lattice search strategy to continuously adjust the key gates in the segment by iteration. Finally, using the asymmetric spatial correlation of CNFET circuits, a grid search strategy is used to iteratively adjust the positions of key gates in the segment to reduce the segment delay. Experimental results on four OpenCores test circuits show that the proposed algorithm improves the circuit timing yield by 20% on average, and reduces the execution time by 25% compared with the CNT density-aware benchmark method, which reveals its potential application in large-scale circuits with high timing yield requirements.