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面向高速PAM4有线收发机的自适应和低复杂度最大似然序列检测器

An Adaptive and Low-Complexity Maximum Likelihood Sequence Detector for High-Speed PAM4 Wireline Transceivers

  • 摘要: 高速串行收发机是中央处理器、网卡和交换机等高性能芯片的关键部件.判决反馈均衡器(decision feedbackequalization,DFE)是高速串行收发机的主要判决电路.针对传统DFE在高码间干扰(intersymbol interference,ISI)信道下的高误码率制约串行收发机速率提升的问题,提出一种面向4电平调制(4 pulse amplitude modulation,PAM4)串行收发机的自适应、低复杂度的减状态序列检测器(adaptive reduced-state sequence detector,ARSSD).ARSSD基于最大似然序列检测结构降低检测误码率;结合Viterbi算法和分区算法降低运算复杂度;采用基于迫零算法的ISI参数获取方式实现检测器参数的自适应更新.所提结构最终完成了行为仿真、电路设计以及系统验证.基于模拟前端芯片和现场可编程门阵列电路的实验结果表明,与传统DFE相比,当12~64 Gbps PAM4信号经过-8~-18 dB@16 GHz衰减信道时,32×4路并行ARSSD检测误码率降低2个数量级,与行为仿真结果一致.

     

    Abstract: The high-speed serial transceiver is the key component for high-performance chips such as CPUs, NICs and switches. The decision feedback equalization (DFE) is the main equalization circuit of the high-speed serial transceiver. However, the high bit error rate (BER) of conventional DFE in high inter-symbol interference (ISI) channels limits the rate increase of serial transceiver. An adaptive reduced-state sequence detector (ARSSD) with low complexity is proposed in this paper. The detector adopts maximum likelihood sequence detection (MLSD) structure to reduce the detection BER, combines the Viterbi algorithm and the set-partitioning algorithm to reduce the complexity of operations and adopts zero-forcing (ZF) algorithm based ISI parameter acquisition to achieve the adaptive detector parameters. In this paper, the behavioral simulation, circuit implementation and system verification of ARSSD are completed. The experimental results based on the analog front-end chip (AFEC) and the field programmable gate array (FPGA) show that: 12~64 Gbps PAM4 signals are faded by -8~-18 dB@16 GHz channel, the detection BER of 32×4 parallel ARSSDs is reduced by two orders of magnitude compared to the conventional DFE, which is consistent with the behavioral simulation results.

     

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