Abstract: The high-speed serial interface is the key core IP component for high-performance chips such as CPUs, NICs and switches. The decision feedback equalization (DFE) is the main decision circuit of the high-speed serial receiver. However, the high bit error rate (BER) of conventional DFE in high inter-symbol inter-ference (ISI) channels limits the rate increase of serial interfaces. An adaptive reduced-state sequence detector (ARSSD) with low complexity is proposed in this paper. The detector adopts maximum likelihood sequence detection (MLSD) structure to reduce the detection BER, combines the Viterbi algorithm and the set-partitioning algorithm to reduce the complexity of operations and adopts zero-forcing (ZF) algorithm based ISI parameter acquisition to achieve the adaptive detector parameters. In this paper, the behavioral simulation, circuit implementation and system verification of ARSSD are completed. The experimental results based on the analog front-end chip (AFEC) and the field programmable gate array (FPGA) show that: 12~64 Gbps PAM4 signals are faded by  8~ 18 dB@16 GHz fading channel, the detection BER of 32×4 parallel ARSSDs is reduced by two orders of magnitude compared to the conventional DFE, which is consistent with the behavioral simulation results.