Abstract: As integrated circuits (ICs) become larger and more complex than ever, to increase design automaticity and productivity, agile design methodology has attracted a lot of attentions. In back-end design of ICs, machine learning technology for agile design are required to build a no-human-in-the-loop RTL-to-GDSII flow. For chip design, timing performance is a critical but effort-taking task. An accurate timing predictor, which is highly correlated with Sign-Off timing, is desirable to guide the timing optimization in the early design process. In this work, we propose a feasible framework for timing optimization in agile design. We also give discussion of the prior researches of machine learning-based timing predictions in RTL to GDSII design process in detail. At last, we further summarize the challenges of timing prediction in agile design from the aspects of data preparation, problem modeling, practicality and generality.